This invention relates to a system for operating a volatile memory in a normal mode and a standby mode, and more particularly, it relates to a system for operating a volatile, dynamic random access memory (RAM) in a normal mode for high speed operation requiring relatively high power and in a standby mode requiring low power consumption.
In general, there does not appear to be any integrated circuit technology available in the prior art which satisfies both the high speed necessary for operating a dynamic random access memory in a normal mode and for operating the memory with low power requirements in a standby mode when the memory is being refreshed from an emergency source of potential such as a battery supported power supply.